Expertise
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ASIC layout: analog & mixed-signal
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Whole chip coverage: from IP blocks to top-level and tape-out
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Strategy design and implementation: ESD, floorplanning, power, padrings
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Physical verification: DRC, LVS, extractions & foundry sign-off
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Context-led design: bonding, encapsulation, packaging & assembly
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Cadence IC6.1, Virtuoso (X)L, kLayout
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Cadence PVS, Assura DRC & LVS
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Calibre DRC & Quantus QRC
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Developmental OS workflows
CAD Experience
Added Value
🌱
Start-up experience
With a decade of being the sole layout engineer within a start-up, I understand the pressures and can deliver to demanding deadlines.
👥
Teamwork
My layout service is a flexible extension to your team. I work as a peer and can mentor less experienced engineers.
🎨
Circuit design knowledge
Simulation is just maths until it meets layout. I can spot design issues before schematic sign-off, saving you time and money.
📦
Assembly & Packaging
I can design your silicon for packaging and assembly from affordable prototyping, through to mass manufacture.
🔬
Microfab experience
My firsthand cleanroom experience gives me insight into DFM that helps your silicon meet specs from your first tape-out.
💡
Novel tech & methods
I'm not fazed by the esoteric. My experience can help you to strike the balance between novelty and industry standards.